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Preliminary Data Sheet October 2001
L9214A/G Low-Cost Ringing SLIC
Introduction
The Agere Systems Inc. L9214 is a subscriber line interface circuit that is optimized to provide a very low-cost solution for short- and medium-loop applications. This device provides the complete set of line interface functionality, including power ringing needed to interface to a subscriber loop. This device has the capability to operate with a VCC supply of 3.3 V or 5 V and is designed to minimize external components required at all device interfaces.
Applications
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Voice over Internet Protocol (VoIP) Cable Modems Terminal Adapters (TA) Wireless Local Loop (WLL) Telcordia TechnologiesTM GR-909 Access Network Termination (NT) PBX Key Systems
Features
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Low-cost solution Onboard ringing generation with software adjustable crest factor switching Flexible VCC options: -- 3.3 V or 5 V VCC -- No -5 V required Power control options: -- Power control resistor -- Automatic battery switch to minimize off-hook power Eight operating states: -- Scan mode for minimal power dissipation -- Forward and reverse battery active -- On-hook transmission states -- Ring mode -- Disconnect mode Low on-hook power: -- 25 mW scan mode -- 165 mW active mode Two SLIC gain options to minimize external components in codec interface Loop start, ring trip, and ground key detectors Programmable current limit On-hook and scan mode line voltage clamp Thermal protection 48-pin MLCC, 32-pin PLCC, and 28-pin SOG (Please contact your Agere Sales Representative for availability) packages
Description
This device is optimized to provide battery feed, ringing, and supervision on short- and medium-loop plain old telephone service (POTS) loops. Supported round trip loop length is up to 1000 . This device provides power ring to the subscriber by the use of line reversal to create either a sine wave ringing signal with a PWM input or a trapezoidal ringing signal with a selectable crest factor from a square wave input. It provides forward and reverse battery feed states, on-hook transmission, a low-power scan state, and a forward disconnect state. The device requires a VCC and line feed battery to operate. VCC may be either a 3.3 V or a 5 V supply. The ringing signal is derived from the high-voltage battery. An automatic battery switch is included to allow for use of a second lower voltage battery in the off-hook mode, thus minimizing short-loop off-hook power consumption and dissipation. If the user desires single battery operation, a power resistor is required to reduce the power dissipation in the SLIC. Loop closure, ring trip, and ground key detectors are available. The loop closure detector has a fixed threshold with hysteresis. The ring trip detector and ground key detector threshold and time constants are externally set. The dc current limit is programmed by an external resistor, the maximum current limit determined by the Vcc supply. The overhead voltage for this device is fixed and the device is capable of supporting 3.17 dB into a 600 load with minimal overhead. The device is offered with two gain options. This allows for an optimized codec interface, with minimal external components regardless of whether a firstgeneration or a programmable third-generation codec is used.
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L9214A/G Low-Cost Ringing SLIC
Preliminary Data Sheet October 2001
Table of Contents
Contents Page Contents Page
Introduction..................................................................1 Features ....................................................................1 Applications...............................................................1 Description ................................................................1 Features ......................................................................4 Description...................................................................4 Architecture Diagram...................................................7 Pin Information ............................................................8 Operating States........................................................12 State Definitions ........................................................12 Forward Active (Fast Polarity Reversal) .................12 Off-hook................................................................12 On-hook................................................................12 Forward Active (Slow Polarity Reversal).................12 Off-hook................................................................12 On-hook................................................................12 Reverse Active (Fast Polarity Reversal) .................13 Off-hook................................................................13 On-hook................................................................13 Reverse Active (Slow Polarity Reversal) ................13 Off-hook................................................................13 On-hook................................................................13 Scan........................................................................13 Disconnect ..............................................................13 Ring.........................................................................13 Thermal Shutdown..................................................13 Absolute Maximum Ratings.......................................14 Electrical Characteristics ...........................................15 Test Configurations ...................................................22 Applications ...............................................................24 Power Control .........................................................24 dc Loop Current Limit..............................................25 Overhead Voltage ...................................................25 Active Mode .........................................................25 Scan Mode ...........................................................25 On-Hook Transmission Mode...............................25 Ring Mode............................................................26
Loop Range ........................................................... 26 Battery Reversal Rate ............................................ 26 Supervision............................................................... 27 Loop Closure.......................................................... 27 Ring Trip ................................................................ 27 Tip or Ring Ground Detector .................................. 27 Power Ring ............................................................ 27 Periodic Pulse Metering (PPM) ................................ 29 ac Applications ......................................................... 29 ac Parameters........................................................ 29 Codec Types .......................................................... 29 First-Generation Codecs ..................................... 29 Third-Generation Codecs .................................... 29 ac Interface Network .............................................. 29 Design Examples ................................................... 30 First-Generation Codec ac Interface Network--Resistive Termination ...................... 30 Example 1, Real Termination .............................. 31 First-Generation Codec ac Interface Network--Complex Termination ....................... 34 Complex Termination Impedance Design Example............................................................ 34 ac Interface Using First-Generation Codec ......... 33 Transmit Gain...................................................... 35 Receive Gain....................................................... 36 Hybrid Balance .................................................... 36 Blocking Capacitors............................................. 37 Third-Generation Codec ac Interface Network--Complex Termination ....................... 40 Outline Diagram........................................................ 41 28-Pin SOG............................................................ 42 32-Pin PLCC .......................................................... 43 48-Pin MLCC.......................................................... 44 48-Pin MLCC, JEDEC MO-220 VKKD-2................ 45 Ordering Information................................................. 46
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Preliminary Data Sheet October 2001
L9214A/G Low-Cost Ringing SLIC
Table of Contents (continued)
Figures Page Tables Page
Figure 1. Architecture Diagram ...................................7 Figure 2. 28-Pin SOG Diagram ..................................8 Figure 3. 32-Pin PLCC Diagram .................................8 Figure 4. 48-Pin MLCC Diagram .................................9 Figure 5. Basic Test Circuit (3 REN Configuration) ..22 Figure 6. Metallic PSRR ...........................................23 Figure 7. Longitudinal PSRR ....................................23 Figure 8. Longitudinal Balance .................................23 Figure 9. ac Gains ....................................................23 Figure 10. Ringing Waveform Crest Factor = 1.6 .....27 Figure 11. Ringing Waveform Crest Factor = 1.2 .....27 Figure 12. Ring Operation ........................................28 Figure 13. ac Equivalent Circuit ................................31 Figure 14. Agere T7504 First-Generation Codec; Resistive Termination (5 REN Configuration)...........................................32 Figure 15. Interface Circuit Using First-Generation Codec (Blocking Capacitors Not Shown) ..............................................35 Figure 16. ac Interface Using First-Generation Codec (Including Blocking Capacitors) for Complex Termination Impedance ......37 Figure 17. Agere T7504 First-Generation Codec; Complex Termination with Power Control Resistor (3 REN Configuration)................38 Figure 18. Third-Generation Codec ac Interface Network; Complex Termination (3 REN Configuration)...........................................40
Table 1. Pin Descriptions ......................................... 10 Table 2. Control States ............................................ 12 Table 3. Typical Operating Characteristics .............. 14 Table 4. Thermal Characteristics.............................. 14 Table 5. Environmental Characteristics ................... 15 Table 6. 5.0 V Supply Currents ............................... 15 Table 7. 5. 0 V Powering .......................................... 15 Table 8. 3.3 V Supply Currents ................................ 16 Table 9. 3.3 V Powering .......................................... 16 Table 10. Two-Wire Port .......................................... 17 Table 11. Analog Pin Characteristics ...................... 18 Table 12. ac Feed Characteristics ........................... 19 Table 13. Logic Inputs and Outputs (VCC = 5.0 V) .............................................. 20 Table 14. Logic Inputs and Outputs (VCC = 3.3 V) ............................................ 20 Table 15. Ringing Specifications ............................. 20 Table 16. Ring Trip (3 REN Configuration) .............. 21 Table 17. Ring Trip (5 REN Configuration)............... 21 Table 18. Typical Active Mode On- to Off-Hook Tip/Ring Current-Limit Transient Response ................................................ 25 Table 19. FB1/FB2 Values vs. Typical Ramp Time at VBAT1 = -65 V ....................................... 26 Table 20. L9214 Parts List for Agere T7504 First-Generation Codec; Resistive Termination .............................................. 33 Table 21. L9214 Parts List for Agere T7504 FirstGeneration Codec; Complex Termination with Power Control Resistor .................... 38 Table 22. L9214 Parts List for Agere T8536 Third-Generation Codec Meter Pulse Application ac and dc Parameters; Fully Programmable ................................ 41
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L9214A/G Low-Cost Ringing SLIC
Preliminary Data Sheet October 2001
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Features
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Onboard balanced trapezoidal ringing generation, 40 Vrms, 1.2 crest factor: -- 3 REN ring load (2330 + 24 F), 600 loop -- 2 REN ring load (3500 + 16 F), 1000 loop -- 2 REN ring load (3500 + 1.8 F), 500 loop -- No ring relay -- No bulk ring generator required -- 15 Hz to 70 Hz ring frequency supported Power supplies requirements: -- VCC talk battery and ringing battery required -- No -5 V supply required -- No high-voltage positive supply required Flexible Vcc options: -- 3.3 V or 5 V VCC operation -- 3.3 V or 5 V VCC interchangeable and transparent to users Power control options: -- Automatic battery switch -- Power control resistor Minimal external components required Ten operating states: -- Forward active, fast polarity reversal -- Reverse active, fast polarity reversal -- Forward active, slow polarity reversal -- Reverse active, slow polarity reversal -- Scan -- Disconnect -- Ringing, line forward with high slope -- Ringing, line reverse with high slope -- Ringing, line forward with low slope -- Ringing, line reverse with low slope Unlatched parallel data control interface Low SLIC power: -- Scan 24 mW (VCC = 5.0 V) -- Forward/reverse active 148 mW (VCC = 5.0 V) -- Scan 17 mW (VCC = 3.3 V) -- Forward/reverse on-hook 135 mW (VCC = 3.3 V) Supervision: -- Loop start, fixed threshold with hysteresis -- Ring trip filtering, fixed threshold not a function of battery voltage, user adjustable with an external resistor -- Common-mode current for ground key applications, user-adjustable threshold Adjustable current limit: -- 10 mA to 45 mA programming range at 5 V Vcc -- 10 mA to 35 mA programming range at 3.3 V Vcc
Overhead voltage: -- Automatically adjusted in active mode -- Clamped <56.5 V in scan and on-hook modes Thermal shutdown protection with hysteresis Longitudinal balance: -- ETSI/ITU-T balance -- GR-909 Meter pulse compatible ac interface: -- Two SLIC gain options to minimize external components required for interface to first- or third-generation codecs -- Sufficient dynamic range for direct coupling to codec output 28-pin SOG, 32-pin PLCC, and 48-pin MLCC package options 90 V CBIC-S technology
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Description
The L9214 is designed to provide battery feed, ringing, and supervision functions on short and medium plain old telephone service (POTS) loops. Supported roundtrip loop length is up to 1000 of wiring resistance plus handset or ringing load. This device is designed to minimize power in all operating states. The L9214 offers eight operating states. The device assumes use of a lower-voltage talk battery, a highervoltage ringing battery and a single VCC supply. The L9214 requires only a positive VCC supply. No -5 V supply is needed. The L9214 can operate with a VCC of either 5.0 V or 3.3 V, allowing for greater user flexibility. The choice of VCC voltage is transparent to the user; the device will function with either supply voltage connected. Two batteries may be used: 1. A high-voltage ring battery (VBAT1). VBAT1 is a maximum -70 V and is used for power ringing, scan, and on-hook transmission modes. This supply is current limited to the maximum power ringing current of approximately 90 mApeak. 2. A lower-voltage talk battery (VBAT2). VBAT2 is normally used for active mode powering. Alternatively, operation may be from a single high-voltage battery supply with a power control resistor to reduce the power dissipation in the SLIC.
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Preliminary Data Sheet October 2001
L9214A/G Low-Cost Ringing SLIC
halted to enable on-hook transmission. The ring trip detector and common-mode current detector are active during the ring mode. The user may adjust the crest factor of the ring signal by selecting one of the two slew rates. The two rates, high or low, allow the designer to chose one set of external capacitors to meet the crest factor range of 1.2 to 1.6 over a 3:1 frequency range by software control alone. For increased power efficiency, the crest factor should be kept as low as possible. With maximum VBAT1, the L9214 has sufficient power to ring a 3 REN (2310 + 24 F) ringing load into 600 of physical wiring resistance. With maximum VBAT1, the L9214 has sufficient power to ring a 2 REN (3500 + 16 F) ringing load into <1000 of physical wiring resistance. Loop ranges may be expanded by applying a lower crest factor trapezoidal input waveform. This feature eliminates the need for a separate external ring relay, associated external circuitry, and a bulk ringing generator. See the Applications section of this data sheet for more information. Where PPM is required, it is injected into the audio receive pins (ac-coupled). PPM shaping must be done externally and the PPM level must be within the 1.12 Vrms (3.17 dBm, 600 ) level set by the amplifier overhead in the active state. Both the ring trip and loop closure supervision functions are included. The loop closure has a fixed typical 10 mA on- to off-hook threshold in the active and scan mode. In either case, there is a 2 mA hysteresis. The ring trip detector requires a simple filter at the input. The ring trip threshold internally at a given battery voltage is fixed, but the threshold can be adjusted through an external voltage divider. Typical ring trip threshold is 20.1 mA for a -65 V VBAT1. A common-mode current detector for tip or ring ground detection is included for ground key applications. The threshold is user programmable via external resistors. See the Applications section of this data sheet for more information on supervision functions.
Description (continued)
Forward and reverse battery active modes are used for off-hook conditions. Since this device is designed for short- and medium-loop applications, the lower-voltage VBAT2 is normally applied during the forward and reverse active states. Battery reversal is quiet, without breaking the ac path. The rate of battery reversal may be ramped to control switching time. The magnitude of the overhead voltage in the forward and reverse active modes allows for an undistorted signal of 3.17 dBm into 600 . The ring trip detector is turned off during active modes to conserve power. On-hook transmission is not permitted in the scan mode. In this mode, the tip ring voltage is derived from the higher VBAT1 rather than VBAT2. In the scan and active modes, the overhead voltage is set such that the tip/ring open loop voltage is 42.5 V minimum for a primary battery of 63 V to 70 V for compatibility with maintenance termination units (MTUs). Also, the maximum voltage with respect to ground (tip or ring to ground) is 56.5 V to comply with ULTM 1950/60950 ANNEX M.2 method B and IEC(R) 60950 (quiet interval of ringing). If the primary battery is below -63 V, the magnitude of the tip/ring open circuit voltage is approximately 17 V less than the battery. To minimize on-hook power, a low-power scan mode is available. In this mode, all functions except off-hook supervision are turned off to conserve power. On-hook transmission is not allowed in the scan mode. A forward disconnect mode is provided, where all circuits are turned off and power is denied to the loop. The device offers a ring mode, in which a power ring signal is provided to the tip/ring pair. During the ring mode, the user, by use of the input states, performs line reversals at the required frequency, which generates the power ringing signal. This signal may be applied continuously but is normally cadenced to meet country-specific requirements. The input states are normally set to an active state when power ringing is
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L9214A/G Low-Cost Ringing SLIC
Preliminary Data Sheet October 2001
A receive gain of 2 is more appropriate when choosing a third-generation type codec. Third-generation codecs will synthesize termination impedance and set hybrid balance and overall gains. To accomplish these functions, third-generation codecs typically have both analog and digital gain filters. For optimal signal to noise performance, it is best to operate the codec at a higher gain level. If the SLIC then provides a high gain, the SLIC output may be saturated causing clipping distortion of the signal at tip and ring. To avoid this situation, with a higher gain SLIC, external resistor dividers are used. These external components are not necessary with the lower gain offered by the L9214. See the Applications section of this data sheet for more information. The L9214 is internally referenced to 1.5 V. The SLIC output VITR is referenced to AGND; therefore, it must be ac-coupled to the codec input. However, the SLIC inputs RCVP/RCVN are floating inputs. If there is not feedback from RCVP/RCVN to VITR, RCVP/RCVN may be directly coupled to the codec output. If there is feedback from RCVP/RCVN to VITR, RCVP/RCVN must be ac coupled to the codec output. The L9214 is thermally protected to guard against faults. Upon reaching the thermal shutdown temperature, the device will enter an all-off mode. Upon cooling, the device will re-enter the state it was in prior to thermal shutdown. Hysteresis is built in to prevent oscillation. The L9214 is packaged in the 28-pin SOG, 32-pin PLCC and 48-pin MLCC surface-mount packages. The L9214A is set for gain of eight applications, and the L9214G is set for gain of two applications.
Description (continued)
Longitudinal balance is consistent with European ETSI and North American GR-909 requirements. Specifications are given in Table 10. Data control is via a parallel unlatched control scheme. The dc current limit is programmable in the active modes by use of an external resistor connected between DCOUT and IPROG. Design equations for this feature are given in the dc Loop Current Limit section within the Applications section of this data sheet. Programming range is 15 mA to 45 mA with VCC = 5.0 V and 15 mA to 35 mA with VCC = 3.3 V. Programming accuracy is 10% over this current range. Circuitry is added to the L9214 to minimize the inrush of current from the VCC supply and to the battery supply during an on- to off-hook transition, thus saving in power supply design cost. See the Applications section of this data sheet for more information. Transmit and receive gains have been chosen to minimize the number of external components required in the SLIC-codec ac interface, regardless of the choice of codec. The L9214 uses a voltage feed-current sense architecture; thus, the transmit gain is a transconductance. The L9214 transconductance is set via a single external resistor, and this device is designed for optimal performance with a transconductance set at 300 V/A. The L9214 offers an option for a single-ended to differential receive gain of either 8 or 2. These options are mask programmable at the factory and are selected by choice of product code. A receive gain of 8 is more appropriate when choosing a first-generation type codec where termination impedance, hybrid balance, and overall gains are set by external analog filters. The higher gain is typically required for synthesization of complex termination impedance.
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Preliminary Data Sheet October 2001
L9214A/G Low-Cost Ringing SLIC
Architecture Diagram
AGND
VCC
BGND VBAT2
VBAT1
IPROG
NSTAT
RTFLT
DCOUT
IREF VITR POWER/BATTERY SWITCH
CURRENT LIMIT AND INRUSH CONTROL
RING TRIP
X20 AAC TXI ITR - VTX AX + (ITR/308) VREF REFERENCE CIRCUIT VTX
LOOP CLOSURE COMMONMODE CURRENT DETECTOR ICM TRGDET
RECTIFIER
X1
CF2
RFT PT ITR 18
- + VBAT1 VBAT2 X1 CF1 FB2 FB1
TIP/RING CURRENT SENSE ITR PR
RFR 18
+ - VBAT1 VBAT2 ac INTERFACE
- GAIN + 9214A GAIN = 4 PARALLEL DATA INTERFACE 9214G GAIN = 1
RCVN RCVP
B0
B1
B2
B3 12-3530.C (F)
Figure 1. Architecture Diagram
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L9214A/G Low-Cost Ringing SLIC
Preliminary Data Sheet October 2001
Pin Information
NSTAT VITR RCVP RCVN DCOUT IPROG CF2 CF1 RTFLT IREF AGND VCC VBAT1 VBAT2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 L9214 28-PIN SOG
28 27 26 25 24 23 22 21 20 19 18 17 16 15
TXI VTX ITR B0 B1 B2 B3 PR PT FB1 FB2 ICM TRGDET BGND
12-3568 (F)
Figure 2. 28-Pin SOG Diagram
NSTAT
RCVP
VITR
VTX 31
4 RCVN NC NC NC DCOUT IPROG CF2 CF1 RTFLT 5 6 7 8 9 10 11 12 13 14 IREF
3
2
1
32
30 29 28 27 26 B0 B1 B2 B3 PR PT FB1 FB2 ICM
L9214 32-PIN PLCC
ITR 25 24 23 22 21 20 TRGDET
15 AGND
16 VCC
17 VBAT1
18 VBAT2
TXI
NC
19 BGND
Figure 3. 32-Pin PLCC Diagram
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Preliminary Data Sheet October 2001
L9214A/G Low-Cost Ringing SLIC
Pin Information (continued)
NSTAT
RCVN
RCVP
VITR
VTX
ITR
TXI
NC
NC
NC
NC
48 47 46 45 44 43 42 41 40 39 38 37 NC NC NC NC NC DCOUT IPROG NC CF2 CF1 NC RTFLT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 VBAT1 AGND VBAT2 TRGDET BGND VCC ICM IREF NC NC NC NC L9214A/G 48-PIN MLCC 36 35 34 33 32 31 30 29 28 27 26 25 B0 B1 B2 B3 NC PR NC PT NC NC FB1 FB2
NC
12-3361f(F)
Figure 4. 48-Pin MLCC Diagram
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L9214A/G Low-Cost Ringing SLIC
Preliminary Data Sheet October 2001
Pin Information (continued)
Table 1. Pin Descriptions 28-Pin SOG 1 32-Pin PLCC 1 48-Pin MLCC 43 Symbol NSTAT Type O Name/Function Loop Closure Detector Output--Ring Trip Detector Output. When low, this logic output indicates that an offhook condition exists or ringing is tripped. No Connection. May be used as a tie point.
--
--
2
5, 14, 18, 28, 32, 39, 42, 44 2, 6, 7, 8 1--4, 8, 11, 17, 21, 27, 30, 37, 46 3 45
--
NC
--
NC
--
No Connection. May not be used as a tie point.
VITR
O
3
4
47
RCVP
I
4
5
48
RCVN
I
5
9
6
DCOUT
O
6
10
7
IPROG
I
7 8 9
11 12 13
9 10 12
CF2 CF1 RTFLT
-- -- --
10
14
13
IREF
I
11 12 13 14 15
15 16 17 18 19
15 16 19 20 22
AGND VCC VBAT1 VBAT2 BGND
GND PWR PWR PWR GND
Transmit ac Output Voltage. Output of internal AAC amplifier. This output is a voltage that is directly proportional to the differential ac tip/ring current. Receive ac Signal Input (Noninverting). This highimpedance input controls to ac differential voltage on tip and ring. This node is a floating input. Receive ac Signal Input (Inverting). This high-impedance input controls to ac differential voltage on tip and ring. This node is a floating input. dc Output Voltage. This output is a voltage that is directly proportional to the absolute value of the differential tip/ring current. This is used to set the dc current limit and the ring trip threshold. Current-Limit Program Input. A resistor is connected from this pin to DCOUT to program the dc current limit for the device. Filter Capacitor. Connect a capacitor from this node to ground. Filter Capacitor. Connect a capacitor from this node to CF2. Ring Trip Filter. Connect this lead to DCOUT via a resistor and to AGND with a capacitor or a resistor capacitor combination, depending on the ringing type, to filter the ring trip circuit to prevent spurious responses. SLIC Internal Reference Current. Connect a resistor between this pin and AGND to generate an internal reference current. Analog Signal Ground. Analog Power Supply. User choice of 5 V or 3.3 V nominal power supply. Battery Supply 1. High-voltage battery. Battery Supply 2. Low-voltage battery or power control resistor. Battery Ground. Ground return for the battery supplies.
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Preliminary Data Sheet October 2001
L9214A/G Low-Cost Ringing SLIC
Pin Information (continued)
Table 1. Pin Descriptions (continued) 28-Pin SOG 16 32-Pin PLCC 20 48-Pin MLCC 23 Symbol TRGDET Type O Name/Function Tip/Ring Ground Detect. When high, this open collector output indicates the presence of a ring ground or a tip ground. This supervision output may be used in ground key or common-mode fault detection applications. Common-Mode Current Sense. To program tip or ring ground sense threshold, connect a resistor to VCC and connect a capacitor to AGND to filter 50/60 Hz. If unused, the pin is connected to ground. Polarity Reversal Slowdown Capacitor. Connect a capacitor from this node for controlling rate of battery reversal. Also used for ringing, this pin cannot be left open. Polarity Reversal Slowdown Capacitor. Connect a capacitor from this node for controlling rate of battery reversal. Also used for ringing, this pin cannot be left open. Protected Tip. The input to the loop sensing circuit and output drive of the tip amplifier. Connect to loop through overvoltage and overcurrent protection. Protected Ring. The input to the loop sensing circuit and output drive of the ring amplifier. Connect to loop through overvoltage and overcurrent protection. State Control Input. State Control Input. State Control Input. State Control Input. Transmit Gain. Input to AX amplifier. Connect a resistor from this node to VTX to set transmit gain. Gain shaping for termination impedance with a COMBO I codec is also achieved with a network from this node to VTX. ac/dc Output Voltage. Output of internal AX amplifier. The voltage at this pin is directly proportional to the differential tip/ring current. ac/dc Separation. Input to internal AAC amplifier. Connect a 0.1 F capacitor from this pin to VTX.
17
21
24
ICM
I
18
22
25
FB2
--
19
23
26
FB1
--
20
24
29
PT
I/O
21
25
31
PR
I/O
22 23 24 25 26
26 27 28 29 30
33 34 35 36 38
B3 B2 B1 B0 ITR
I I I I I
27
31
40
VTX
O
28
32
41
TXI
I
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L9214A/G Low-Cost Ringing SLIC
Preliminary Data Sheet October 2001
Operating States
Table 2. Control States B3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 State Disconnect Ringing, (line reverse with high slope) Unused* Ringing, (line forward with high slope) Disconnect Reverse active and on-hook, fast polarity reversal Scan Forward active and on-hook, fast polarity reversal Disconnect Ringing, (line reverse with low slope) Unused* Ringing, (line forward with low slope) Disconnect Reverse active and on-hook, slow polarity reversal Scan Forward active and on-hook, slow polarity reversal
* In this state, all supervision functions are disabled, on hook transmission is disabled, pin PT is positive with respect to PR, VBAT1 is applied to tip/ring, and the tip to ring voltage will be equivalent to the scan state.
State Definitions
Forward Active (Fast Polarity Reversal)
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Loop closure and common-mode detect are active. Ring trip detector is turned off to conserve power. On-hook transmission is enabled. Overhead is set to nominal 17.0 V for undistorted transmission of 0 dBm into 600 .
Off-hook
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Pin PT is positive with respect to PR. VBAT2 is applied to tip/ring drive amplifiers for the majority of loop lengths. This may also be derived from VBAT1 through a power control resistor. Loop closure and common-mode detect are active. Ring trip detector is turned off to conserve power. Overhead is set for undistorted transmission of +3.17 dBm into 600 .
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Forward Active (Slow Polarity Reversal)
Off-hook Same as the forward active (fast polarity reversal) state, but with slower polarity reversal.
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On-hook
s
On-hook
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Same as the forward active (fast polarity reversal) state, but with slower polarity reversal.
Pin PT is positive with respect to PR. VBAT1 is applied to tip/ring drive amplifiers. The tip to ring on-hook differential voltage will be between -42.5 V and -56.5 V with a primary battery of -65 V.
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L9214A/G Low-Cost Ringing SLIC
Scan
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State Definitions (continued)
Reverse Active (Fast Polarity Reversal)
Off-hook
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Except for loop closure, all circuits (including ring trip and common-mode detector) are powered down. On-hook transmission is disabled. Pin PT is positive with respect to PR, and VBAT1 is applied to tip/ring. The tip to ring on-hook differential voltage will be between -42.5 V and -56.5 V with a -65 V primary battery.
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Pin PR is positive with respect to PT. VBAT2 is applied to tip/ring drive amplifiers via the soft battery switch for the majority of loop lengths. This may also be derived from VBAT1 through a power control resistor. Loop closure and common-mode detect are active. Ring trip detector is turned off to conserve power. Overhead is set to nominal 4.0 V for undistorted transmission of 0 dBm into 600 and may be increased automatically for larger signal levels.
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Disconnect
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The tip/ring amplifiers and all supervision are turned off. The SLIC goes into a high-impedance state. NSTAT is forced high (on-hook).
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On-hook
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Pin PR is positive with respect to PT. VBAT1 is applied to tip/ring drive amplifiers. The tip to ring on-hook differential voltage will be between -42.5 V and -56.5 V with a primary battery of -65 V. Loop closure and common-mode detect are active. Ring trip detector is turned off to conserve power. On-hook transmission is enabled. Overhead is set to nominal 17.0 V for undistorted transmission of 0 dBm into 600 .
Ring
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Ringing controlled digitally or by a PWM input signal Power ring signal is applied to tip and ring. Software-selectable slew rate, fast or slow. Ring trip supervision and common-mode current supervision are active; loop closure is inactive. Overhead voltage is reduced to typically 2.5 V and current limit set at IPROG is disabled. Current is limited by saturation current of the amplifiers themselves, typically 72 mA peak at 125 C.
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s
s
Reverse Active (Slow Polarity Reversal)
Off-hook
Thermal Shutdown
s
Same as the reverse active (fast polarity reversal) state, but with slower polarity reversal.
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Not controlled via truth table inputs. This mode is caused by excessive heating of the device, such as may be encountered in an extended power-cross situation.
On-hook
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Same as the reverse active (fast polarity reversal) state, but with slower polarity reversal.
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L9214A/G Low-Cost Ringing SLIC
Preliminary Data Sheet October 2001
Absolute Maximum Ratings (at TA = 25 C)
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. Parameter dc Supply (VCC) Battery Supply (VBAT1) Battery Supply (VBAT2) Logic Input Voltage Logic Output Voltage Operating Temperature Range Storage Temperature Range Relative Humidity Range Ground Potential Difference (BGND to AGND) Symbol -- -- -- -- -- -- -- -- -- Min -0.5 -- -- -0.5 -0.5 -40 -40 5 -- Typ -- -- -- -- -- -- -- -- -- Max 7.0 -80 VBAT1 VCC + 0.5 VCC + 0.5 125 150 95 1 Unit V V V V V C C % V
Note: The IC can be damaged unless all ground connections are applied before, and removed after, all other connections. Furthermore, when powering the device, the user must guarantee that no external potential creates a voltage on any pin of the device that exceeds the device ratings. For example, inductance in a supply lead could resonate with the supply filter capacitor to cause a destructive overvoltage.
Table 3. Typical Operating Characteristics Parameter 5 V dc Supplies (VCC) 3 V dc Supplies (VCC) High Office Battery Supply (VBAT1) Auxiliary Office Battery Supply (VBAT2) Operating Temperature Range (28-pin SOG) Operating Temperature Range (32-pin PLCC) Table 4. Thermal Characteristics Parameter Thermal Protection Shutdown (Tjc) 28-pin SOG Thermal Resistance Junction to Ambient (JA)1, 2: Natural Convection 2S2P Board Wind Tunnel 200 Linear Feet per Minute (LFPM) 2S2P Board 32-pin PLCC Thermal Resistance Junction to Ambient (JA)1, 2: Natural Convection 2S2P Board Natural Convection 2S0P Board Wind Tunnel 100 Linear Feet per Minute (LFPM) 2S2P Board Wind Tunnel 100 Linear Feet per Minute (LFPM) 2S0P Board 48-pin MLCC Thermal Resistance Junction to Ambient (JA)1, 2 Min 150 -- -- -- -- -- -- -- Typ 165 70 59 35.5 50.5 31.5 42.5 38 Max -- -- -- -- -- -- -- -- Unit C
C/W C/W C/W C/W C/W C/W C/W
Min -- 2.97 -63 -15 0 -40
Typ 5.0 3.3 -65 -21 25 25
Max 5.25 -- -70 VBAT1 70 85
Unit V V V V C C
1. This parameter is not tested in production. It is guaranteed by design and device characterization. 2. Airflow, PCB board layers, and other factors can greatly affect this parameter.
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Preliminary Data Sheet October 2001
L9214A/G Low-Cost Ringing SLIC
Electrical Characteristics
Table 5. Environmental Characteristics Parameter Temperature Range (28-pin SOG) Temperature Range (32-pin PLCC and 48-pin MLCC) Humidity Range1
1. Not to exceed 26 grams of water per kilogram of dry air.
Min 0 -40 5
Typ -- -- --
Max 70 85 951
Unit C C %RH
Table 6. 5.0 V Supply Currents VBAT1 = -65 V, VBAT2 = -21 V, VCC = 5.0 V. Parameter Supply Currents (scan state; no loop current): IVCC IVBAT1 IVBAT2 Supply Currents (forward/reverse active; no loop current, VBAT1 applied): IVCC IVBAT1 IVBAT2 Supply Currents (disconnect mode): IVCC IVBAT1 IVBAT2 Supply Currents (ringing mode, no load applied): IVCC IVBAT1 IVBAT2 Table 7. 5.0 V Powering VBAT1 = -65 V, VBAT2 = -21 V, VCC = 5.0 V. Parameter Power Dissipation (scan state; no loop current) Power Dissipation (forward/reverse active; no loop current, VBAT1 applied) Power Dissipation (disconnect mode) Power Dissipation (ring mode; no load applied)
Note:
Min -- -- -- -- -- -- -- -- -- -- -- --
Typ 2.90 0.09 0.04 4.8 1.5 1.0 1.60 0.02 0.01 4.40 1.70 0.57
Max 3.80 0.20 0.07 6.00 1.95 1.20 2.20 0.10 0.02 5.0 2.2 0.7
Unit mA mA mA mA mA mA mA mA mA mA mA mA
Min -- -- -- --
Typ 21 143 10 144
Max 33 182 18 183
Unit mW mW mW mW
Refer to the power control description in the Applications section to calculate power dissipation in the forward/reverse off-hook state.
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L9214A/G Low-Cost Ringing SLIC
Preliminary Data Sheet October 2001
Electrical Characteristics (continued)
Table 8. 3.3 V Supply Currents VBAT1 = -65 V, VBAT2 = -21 V, VCC = 3.3 V. Parameter Supply Currents (scan state; no loop current): IVCC IVBAT1 IVBAT2 Supply Currents (forward/reverse active; no loop current, VBAT1 applied): IVCC IVBAT1 IVBAT2 Supply Currents (disconnect mode): IVCC IVBAT1 IVBAT2 Supply Currents (ringing mode, no load applied): IVCC IVBAT1 IVBAT2 Table 9. 3.3 V Powering VBAT1 = -65 V, VBAT2 = -21 V, VCC = 3.3 V. Parameter Power Dissipation (scan state; no loop current) Power Dissipation (forward/reverse active; no loop current, VBAT1 applied) Power Dissipation (disconnect mode) Power Dissipation (ring mode; no loop current)
Note:
Min -- -- -- -- -- -- -- -- -- -- -- --
Typ 2.30 0.09 0.04 4.40 1.50 0.97 1.20 0.02 0.01 4.00 1.64 0.54
Max 3.00 0.18 0.07 5.30 1.90 1.20 1.70 0.10 0.02 4.75 2.16 0.60
Unit mA mA mA mA mA mA mA mA mA mA mA mA
Min -- -- -- --
Typ 14 132 5 131
Max 23 166 13 169
Unit mW mW mW mW
Refer to the power control description in the Applications section to calculate power dissipation in the forward/reverse off-hook state.
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Preliminary Data Sheet October 2001
L9214A/G Low-Cost Ringing SLIC
Electrical Characteristics (continued)
Table 10. Two-Wire Port Parameter Tip or Ring Drive Current = dc + Longitudinal + Signal Currents Tip or Ring Drive Current = Ringing + Longitudinal Signal Current Longitudinal Current Capability per Wire (Longitudinal current is independent of dc loop current.) Ringing Current (RLOAD = 2330 + 24 F) Ringing Current (RLOAD = 3500 + 1.8 F) Ringing Current Limit (RLOAD = 100 ) dc Loop Current--ILIM (RLOOP = 500 ): Programming Range (VCC = 5.0 V) Programming Range (VCC = 3.3 V) dc Current Variation (current limit 15 mA to 45 mA) dc Loop Current (RLOOP = 100 , on to off hook transition) t < 20 ms dc Loop Current (RLOOP = 100 , on to off hook transition) t < 50 ms dc Feed Resistance, 2 x RF (excluding protection resistors) Loop Resistance Range*, (0 dB overload into 600 ) ILOOP = 20 mA, VBAT2 = -24 V, 50 (2 x RF), 60 (2 x RP), 300 RLOOP plus Handset ILOOP = 25 mA, VBAT1 = -65 V, 50 (2 x RF), 60 (2 x RP), 1000 RLOOP plus Handset Open Loop Voltages, |VBAT1| = -63 V to -70 V: Scan/On-Hook Transmission Mode: |PT - PR| - Differential |PT| or |PR| Referenced to BGND Ring Mode, |VBAT1| = -63 V to -70 V: |PT - PR| - Differential, (open loop ring voltage) Loop Closure Threshold: Scan/Active/On-hook Transmission Modes Loop Closure Threshold Hysteresis: Ground Key: Differential Detector Threshold Detection Longitudinal to Metallic Balance at PT/PR Test Method per Figure 8, 1 kHz 58 dB minimum, 60 dB typical: 300 Hz to 600 Hz 600 Hz to 3.4 kHz Metallic to Longitudinal (harm) Balance: 200 Hz to 1000 Hz 100 Hz to 4000 Hz PSRR 500 Hz--3000 Hz: VBAT1, VBAT2 VCC (3.3 V operation) Min 72 37 5 8.5 25 12 -- 15 15 -- -- -- -- -- 25 840 1540 Typ -- -- -- 15 -- -- -- -- -- -- -- -- -- -- 36 -- -- Max -- -- -- -- -- -- 90 45 35 10 350 100 -- 150% 50 -- -- Unit mApeak mApeak mArms mArms mApeak mApeak mApeak mA mA % mApeak mA ILIM

42.5 -- 40 -- -- 5 50
48 -- -- 10 2 8 --
-- 56.5 -- -- -- 10 --
V V Vrms mA mA mA ms
55 55 40 40 40 25
58 58 -- -- -- --
-- -- -- -- -- --
dB dB dB dB dB dB
* Values guaranteed by design, not subject to production test. (R) Corresponds to 55 dB minimum with 1%, 30 resistors per Q552 (11/96) Section 2.1.2 and IEEE 455.
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L9214A/G Low-Cost Ringing SLIC
Preliminary Data Sheet October 2001
Electrical Characteristics (continued)
Table 11. Analog Pin Characteristics Parameter TXI (input impedance) Output Offset (VTX) Output Offset (VITR) Output Drive Current (VTX) Output Drive Current (VITR) Output Voltage Swing (VTX) (VCC = 5.0 V) Output Voltage Swing (VITR) (VCC = 5.0 V) Output Short-circuit Current (VTX) Output Short-circuit Current (VITR) Output Load Resistance (VTX and VITR) Output Load Capacitance (VTX) Output Load Capacitance (VITR) RCVN and RCVP: Input Voltage Range (VCC = 5.0 V) Input Voltage Range (VCC = 3.3 V) Input Bias Current Min -- -- -- -- -- 3.7 -- -- -- 10 -- -- 0 0 -- Typ 100 5 70 500 250 -- -- 5 6 -- -- -- -- -- -- Max -- -- -- -- -- +5/-8 3.1 -- -- -- 20 50 VCC - 0.5 VCC - 0.3 1.5 Unit k mV mV A A V V mA mA k pF pF V V A
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Preliminary Data Sheet October 2001
L9214A/G Low-Cost Ringing SLIC
Electrical Characteristics (continued)
Table 12. ac Feed Characteristics Parameter ac Termination Total Harmonic Distortion (200 Hz--4 kHz)2: Off-hook On-hook Transmit Gain (f = 1004 Hz, 1020 Hz)3: PT/PR Current to VITR Receive Gain4 (f = 1004 Hz to 1020 Hz): RCVP or RCVN to PT--PR (gain of 8 option, L9214A) RCVP or RCVN to PT--PR (gain of 2 option, L9214G) Gain vs. Frequency (transmit and receive)2, 600 Termination (Q.552), 1004 Hz, 1020 Hz reference: 200 Hz--300 Hz 300 Hz--3.4 kHz 3.4 kHz--3.6 kHz 3.6 kHz--20 kHz 20 kHz--266 kHz Gain vs. Level (transmit and receive)2, 0 dBV Reference (Q.552): -55 dB to +3.0 dB Idle-channel Noise (tip/ring) 600 Termination: Psophometric C-Message 3 kHz Flat Idle-channel Noise (VTX) 600 Termination: Psophometric C-Message 3 kHz Flat Impedance1 Min 150 -- -- 291 7.6 1.9 Typ 600 -- -- 300 8 2 Max 1400 0.3 1.0 309 8.4 2.1 Unit
% % V/A -- --
-0.30 -0.05 -1.50 -3.00 -- -0.05 -- -- -- -- -- --
0 0 0 -0.1 -- 0 -82 8 -- -82 8 --
0.05 0.05 0.05 -0.05 -2.0 0.05 -77 13 20 -77 13 20
dB dB dB dB dB dB dBmp dBrnC dBrn dBmp dBrnC dBrn
1. Set externally either by discrete external components or a third- or fourth-generation codec. Any complex impedance R1 + R2 || C between 150 and 1400 can be synthesized. 2. This parameter is not tested in production. It is guaranteed by design and device characterization. 3. VITR transconductance depends on the resistor from ITR to VTX. This gain assumes an ideal 4750 , the recommended value. Positive current is defined as the differential current flowing from PT to PR. 4. Tested per Figure 9. The gain reading is adjusted by the ratio of 696/660 to account for the 36 nominal ac feed resistance.
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L9214A/G Low-Cost Ringing SLIC
Preliminary Data Sheet October 2001
Electrical Characteristics (continued)
Table 13. Logic Inputs and Outputs (VCC = 5.0 V) Parameter Input Voltages: Low Level High Level Input Current: Low Level (VCC = 5.25 V, VI = 0.4 V) High Level (VCC = 5.25 V, VI = 2.4 V) Output Voltages (open collector with internal pull-up resistor): Low Level (VCC = 4.75 V, IOL = 200 A) High Level (VCC = 4.75 V, IOH = -10 A) Table 14. Logic Inputs and Outputs (VCC = 3.3 V) Parameter Input Voltages: Low Level High Level Input Current: Low Level (VCC = 3.46 V, VI = 0.4 V) High Level (VCC = 3.46 V, VI = 2.4 V) Output Voltages (open collector with internal pull-up resistor): Low Level (VCC = 3.13 V, IOL = 200 A) High Level (VCC = 3.13 V, IOH = -5 A) Table 15. Ringing Specifications Parameter Ring Signal Isolation: PT/PR to VITR Ring Mode Ringing Voltage (5 REN 1386 + 40 F load, 200 loop, 2 x 30 protection resistors, -69 V battery, 1.2 crest factor)1 Ringing Voltage (3 REN 2330 + 24 F load, 600 loop, 2 x 30 protection resistors, -69 V battery, 1.2 crest factor)1 Ringing Voltage (2 REN 3500 + 16 F load, 1000 loop, 2 x 30 protection resistors, -69 V battery, 1.2 crest factor)1 Ringing Voltage (2 REN 3500 + 1.8 F load, 500 loop, 2 x 30 protection resistors, -69 V battery, 1.2 crest factor)2 Ring Signal Distortion: 5 REN 1386 , 40 F Load, 200 Loop 3 REN 2330 , 24 F Load, 600 Loop 2 REN 3500 , 16 F Load, 1000 Loop 2 REN 3500 , 1.8 F Load, 500 Loop
1. Voltage is measured across both resistive and capacitive elements of the ringer load. 2. Voltage is measured only across the resistive element of the ringer load.
Symbol VIL VIH IIL IIH VOL VOH
Min -0.5 2.0 -- -- 0 2.4
Typ 0.4 2.4 -- -- 0.2 --
Max 0.7 VCC 250 250 0.4 VCC
Unit V V
A A
V V
Symbol VIL VIH IIL IIH VOL VOH
Min -0.5 2.0 -- -- 0 2.2
Typ 0.2 2.5 -- -- 0.2 --
Max 0.5 VCC 250 250 0.5 VCC
Unit V V
A A
V V
Min --
Typ 60
Max --
Unit dB
40 40 40 40
-- -- -- --
-- -- -- --
Vrms Vrms Vrms Vrms
-- -- -- --
5 5 5 5
-- -- -- 10
% % % %
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Preliminary Data Sheet October 2001
L9214A/G Low-Cost Ringing SLIC
Electrical Characteristics (continued)
Table 16. Ring Trip (3 REN Configuration) Parameter Ring Trip (NSTAT = 0): Loop Resistance (total) Ring Trip (NSTAT = 1): Loop Resistance (total) Ringer Load Trip Time (f = 20 Hz) Ringing will not be tripped by the following loads:
s s
Min 0 10 -- --
Typ -- -- -- --
Max 1000 -- 2330 + 24 F 130
Unit
k -- ms
100 resistor in series with a 2 F capacitor applied across tip and ring. Ring frequency = 17 Hz to 23 Hz. 10 k resistor in parallel with a 4 F capacitor applied across tip and ring. Ring frequency = 17 Hz to 23 Hz.
Table 17. Ring Trip (5 REN Configuration) Parameter Ring Trip (NSTAT = 0): Loop Resistance (total) Ring Trip (NSTAT = 1): Loop Resistance (total) Ringer Load Trip Time (f = 20 Hz) Ringing will not be tripped by the following loads:
s s
Min 0 10 -- --
Typ -- -- -- --
Max 600 -- 1386 + 40 F 150
Unit
k -- ms
100 resistor in series with a 2 F capacitor applied across tip and ring. Ring frequency = 17 Hz to 23 Hz. 10 k resistor in parallel with a 6 F capacitor applied across tip and ring. Ring frequency = 17 Hz to 23 Hz.
Note: Refer to the application section for further description of the 3 REN configuration vs. 5 REN configuration.
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L9214A/G Low-Cost Ringing SLIC
Preliminary Data Sheet October 2001
Test Configurations
133 k
1 F RTFLT 75 k DCOUT 5.76 k IPROG IREF 28.7 k 30 TIP RLOOP 100 /600 30 RING 0.047 F FB2 0.047 F FB1 CF1 0.47 F CF2 0.1 F VBAT2 VBAT1 BGND VCC AGND ICM TRGDET NSTAT B3 B3 B1 B2 B1 B2 B0 B0 PT PR 0.1 F L9214 TXI VTX 4750 ITR VITR VITR RCVP RCVN RCVP RCVN
0.1 F 0.1 F VBAT2 VBAT1 VCC
0.1 F
600 k
0.1 F
VCC
12-3531.j (F)
Figure 5. Basic Test Circuit, VCC = 3.3 V (3 REN Configuration)
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Preliminary Data Sheet October 2001
L9214A/G Low-Cost Ringing SLIC
Test Configurations (continued)
VBAT OR VCC 100 4.7 F VS VBAT OR VCC TIP DISCONNECT BYPASS CAPACITOR
VS 100 F TIP 368 BASIC TEST CIRCUIT 368 RING 100 F VITR
+
600 VT/R
BASIC TEST CIRCUIT
LONGITUDINAL BALANCE = 20log
VS VITR
12-2584.D (F)
-
RING
Figure 8. Longitudinal Balance
VS VT/R
12-2582.c (F)
PSRR = 20log
Figure 6. Metallic PSRR
+
VBAT OR VCC 100 4.7 F VS VBAT OR VCC 67.5 TIP 10 F + VM - 67.5 56.3 10 F PSRR = 20log VS VM
12-2583.b (F)
PT 600 VT/R BASIC TEST CIRCUIT RCVN OR RCVP
VITR
DISCONNECT BYPASS CAPACITOR
-
PR
RCVN OR RCVP VS
VXMT GXMT = -----------VT R VT R GRCV = -----------------------------------------------VRCVP OR VRCVN
12-2587.J (F)
BASIC TEST CIRCUIT RING
Figure 9. ac Gains
Figure 7. Longitudinal PSRR
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L9214A/G Low-Cost Ringing SLIC
Preliminary Data Sheet October 2001
Typically IBIAS is 3.5 mA. This additional VBAT1 current contributes to the loop current and the remaining loop current is supplied by VBAT2, so that IVBAT2 = IQ2 + ILOOP - IBIAS
Applications
Power Control
Under normal device operating conditions, power dissipation must be controlled to prevent the device temperature from rising too close to the thermal shutdown point. Power dissipation is highest with higher battery voltages, higher current limit, and under shorter dc loop conditions. Additionally, higher ambient temperature will reduce thermal margin. Increasing the number of PC board layers and increasing airflow around the device are typical ways of improving thermal margin. The maximum recommended junction temperature for the L9214 is 150 C. The junction temperature is: Tj = TAMBIENT + JA * PSLIC The thermal impedance of this device depends on the package type as well as number of PCB layers and airflow. The thermal impedance of the 28-pin SOG package is somewhat higher than the 32-pin PLCC package. The 28-pin SOG package in still air with a single-sided PCB is rated at 70 C/W. The 32-pin PLCC package thermal impedance with no airflow on a four-layer PCB is estimated at 37 C/W. The power handling capability of the package is: PSLIC = (150 C - TAMBIENT)/JA which is a minimum of 0.93 W for the 28-pin SOG package with a single-sided PCB and no airflow and as much as 2.15 W for the 32-pin PLCC package with a multilayer PCB. This device is intended to operate with a high-voltage primary battery of -63 V to -70 V. Under short-loop conditions, an internal soft battery switch shunts most (all but IBIAS = 3.5 mA) of the loop current to an auxiliary battery of lower absolute voltage (typically -21 V). Where single battery operation is required, an external power control resistor can be connected from the VBAT2 pin to VBAT1 and all but 3.5 mA of the loop current will flow through the power control resistor. The power dissipated in the device is best illustrated by an example. Assume VBAT1 is -65 V, VBAT2 is -21 V, and the current limit is is ILOOP. Let IQ1 and IQ2 be the quiescent currents drawn from VBAT1 and VBAT2 respectively (the current drawn from the battery when the phone is on-hook). Let IBIAS be the additional current drawn from VBAT1 when the phone is off-hook. IBIAS = IVBAT1(off-hook) - IQ1
IVCC is the current drawn from VCC and is relatively constant as the phone goes off hook. The total power from the power supplies is: PTOTAL = {[(IQ1 + IBIAS) * VBAT1] + [(IQ2 + ILOOP - IBIAS) * VBAT2] + [(IVCC) * VCC]} The maximum values of IQ1 and IQ2 are 1.95 mA and 1.20 mA respectively from Table 4. If the current limit is set to 25 mA, given the current limit tolerance of 10%, the maximum current limit is 27.5 mA. Also, assume 20 of wire resistance, 30 of protection resistance, and 200 for the handset PTOTAL = {[(1.95 mA + 3.5 mA) * (65 V)] + [(1.20 mA + 27.5 mA - 3.5 mA) * (21 V)] + [(6 mA) * (5 V)] = 913.45 mW The power delivered to the loop and the protection resistors (PLOOP) is: PLOOP = {(ILOOP)2 * [(2 * RPROTECTION) + (RWIRE) + (RPHONE)]} = {(27.5 mA)2 * [(2 * 30 ) + (20 ) + 200 )]} = 212 mW Thus, the total power dissipated by the SLIC is: PD of SLIC = Total power (PTOTAL) - power delivered to loop and protection resistors (PLOOP). PD = 913.45 mW - 212 mW = 701.45 mW for this example. Since the minimum power handling capability of the 28-pin SOG package is 0.93 W, in this case either package type is acceptable even with a single-sided PCB. At higher battery voltages, higher ambient temperature, and higher current limit, the required thermal impedance drops and the 32-pin PLCC package, more PCB layers, or some airflow might be required. Another case to consider is the case of the power control resistor. In this case, the effective VBAT2 voltage is: VBAT2 = VBAT1 - RPWR * (ILOOP - IBIAS + IQ2) For the case of the 27.5 mA maximum current limit, choosing RPWR = 1.75 k would give VBAT2 = -21 V and the same SLIC power as above. The power in the resistor would be: PRPWR = (ILOOP - IBIAS + IQ2)2 * RPWR = 1.11 W Choosing a larger RPWR would result in lower VBAT2 and lower SLIC power, but more power in the resistor. Similarly, choosing a smaller RPWR results in higher VBAT2, higher SLIC power, and less power in the resistor. Agere Systems Inc.
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Preliminary Data Sheet October 2001
L9214A/G Low-Cost Ringing SLIC
The default overhead provides sufficient headroom for on-hook transmission of a +3.17 dBm signal into 600 . +3.17 dBm = 10 log (Vrms2 / P0 * R600 )
Applications (continued)
dc Loop Current Limit
In the active modes, dc current limit is programmable via an external resistor. The resistor is connected between IPROG and DCOUT. The loop current limit (ILOOP) with 100 load is related to the RIPROG programming resistor by: ILOOP (mA) = 4 mA/k * RIPROG (k) + 2 mA Note that the overall current-limit accuracy achieved will be affected by the specified accuracy of the internal SLIC current-limit circuit and the accuracy of the external resistor. The above equation describes the active mode steadystate current-limit response. There will be a transient response of the current-limit circuit upon an on- to offhook transition. Typical active mode transient currentlimit response is given in Table 18. Table 18. Typical Active Mode On- to Off-Hook Tip/ Ring Current-Limit Transient Response Parameter dc Loop Current: Active Mode RLOOP = 100 On- to Off-hook Transition t < 20 ms dc Loop Current: Active Mode RLOOP = 100 On- to Off-hook Transition t < 30 ms dc Loop Current: Active Mode RLOOP = 100 On- to Off-hook Transition t < 50 ms Value ILOOP + 60 Unit mA
dBm = 10 log (Vrms2 / 0.001 W * 600 ) Vrms +3.17 dBm = 10 log ------------------------------0.6 ( IV x R ) Vrms = 1.12 V and Vpeak = 1.58 V are supported. Scan Mode If the magnitude of the primary battery is greater than a nominal -63 V, the magnitude of the open-loop tip to ring voltage is clamped to between -42.5 V and -56.5 V. Again, the overhead is not symmetrical with respect to tip and ring. With the magnitude of the primary battery greater than a nominal -63 V, the tip to ground voltage is clamped between -0.1 V and -0.6 V and the ring to ground voltage is clamped between -42.5 V and -56.5 V. If the magnitude of the primary battery is less than a nominal -63 V, the tip to ground voltage is -0.1 V to -0.6 V and the ring to battery voltage is typically 17 V less than VBAT1. On-Hook Transmission Mode
2
ILOOP + 20
mA If the magnitude of the primary battery is greater than 63 V, the magnitude of the open-loop tip to ring voltage will be greater than 42.5 V. If the magnitude of the primary battery is less than 63 V, the open-loop voltage may be less than 42.5 V and is approximately 17 V less than the magnitude of the primary battery voltage. For primary battery voltages less than 70 V, the magnitude of the ring to ground voltage will be less than 56.5 V. Again, the overhead is not symmetrical with respect to tip and ring. The tip voltage to ground is between -2 V and -4.5 V and the ring to primary voltage is 14.5 V typical.
ILOOP
mA
Overhead Voltage
Active Mode The overhead is preprogrammed in the active mode. Note that overhead is not symmetrical with respect to tip and ring. Under default conditions, the tip to ground voltage is 2.1 V to 2.6 V and the ring to battery overhead is 14.5 V typical.
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L9214A/G Low-Cost Ringing SLIC
Preliminary Data Sheet October 2001
The point of change over between VBAT2 and VBAT1 occurs at: |VBAT2| - (0.9 + 2.5) V > [(2RP + RDC + RL) * ILOOP] V VBAT2 is typically applied under off-hook conditions for power conservation and SLIC thermal considerations. The L9214 is intended for short- and medium-loop applications and, therefore, will always be in current limit during off-hook conditions. However, note that the ringing loop length rather than the dc loop length will be the factor to determine operating loop length. Where VBAT2 is insufficient to support the loop length, the power will be taken from VBAT1.
Applications (continued)
Overhead Voltage (continued)
Ring Mode In the ring mode, to maximize ringing loop length, the overhead is decreased to the saturation of the tip ring drive amplifiers, a nominal 4 V. The tip to ground voltage is 1 V, and the ring to VBAT1 voltage is 3 V. The AX amplifier at VTX is active during the ring mode, differential ring current may be sensed at VTX during the ring mode.
Loop Range
The dc loop range for medium-loop applications is calculated using: ( VBAT1 - VOHH ) RL = ---------------------------------------------- - 2RP - Rdc ILOOP The dc loop range for short-loop applications is calculated using:
( VBAT2 - VOHL ) RL = --------------------------------------------- - 2RP - Rdc ILOOP
Battery Reversal Rate
The rate of battery reverse is controlled or ramped by capacitors FB1 and FB2. A chart showing FB1/FB2 values versus typical ramp time is given below. Leave FB1 and FB2 open if it is not desired to ramp the rate of battery reversal. Table 19. FB1/FB2 Values vs. Typical Ramp Time at VBAT1 = -65 V CFB1/CFB2 0.01 F 0.1 F 0.22 F 0.47 F 1.0 F 1.22 F 1.3 F 1.4 F 1.6 F Transition Time Fast, B3 = 0 7 ms 75 ms 145 ms 300 ms 600 ms 750 ms 830 ms 900 ms 1070 ms Transition Time Slow, B3 = 1 20 ms 220 ms 440 ms 900 ms 1.8 s 2.25 s 2.5 s 2.7 s 3.2 s
where: VOHH = 19.5 (2.5 V + 17 V) and VOHL = 3.4 V (2.5 V + 0.9 V) and where: RL = loop resistance, not including protection resistors. RP = protection resistor value. Rdc = SLIC internal dc feed resistance. |VBAT1| and |VBAT2| = battery voltage magnitude. ILOOP = loop current. VOHH = overhead voltage when power is drawn from VBAT1. VOHL = overhead voltage when power is drawn from VBAT2.
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Preliminary Data Sheet October 2001
L9214A/G Low-Cost Ringing SLIC
use of the state input pins. It is possible to select either fast or slow slew rates to alter the crest factor of the ringing signal. This allows designers to set the external capacitors to a specific factor and change the ringing frequency under software control while maintaining the crest factor between 1.2 and 1.6 for the trapezoidal signal. During the ring mode, it is also possible to supply a pulse-width modulated, PWM, signal into the device's B1 input. This signal is used to produce the power ring signal. This signal must be removed during nonring mode states. The user may input any crest factor ring signal using this method; thus, the device will support a sine wave (crest factor 1.414) or a lower or higher crest factor input for increased power efficiency ring signal. Various crest factors are shown below.
80
Supervision
The L9214 offers the loop closure and ring trip supervision functions. Internal to the device, the outputs of these detectors are multiplexed into a single package output, NSTAT. Additionally, a common-mode current detector for tip or ring ground detection is included for ground key applications.
Loop Closure
The loop closure has a fixed typical 10 mA on- to offhook threshold in the active mode and a fixed 10 mA on- to off-hook threshold from the scan mode. In either case, there is a 2 mA hysteresis with VCC = 5.0 V and with VCC = 3.3 V.
Ring Trip
The ring trip detector requires an external filter at the input, minimizing external components. An R + R//C combination of 75 k and 133 k // 1 F, for a filter pole at 3.3 Hz, is recommended for a 3 REN configuration. For a 5 REN configuration, a 150 k and 100 k // 1 F (for a filter pole at 2.65 Hz) combination is recommended. The ring trip threshold is internally fixed and is independent of battery voltage. The threshold, IRT = 20.1 mA.
VOLTS (V)
60 40 20 0 -20 -40 -60 -80 0.00 0.04 0.08 0.12 0.16 0.20 0.02 0.06 0.10 0.14 0.18 TIME (s)
12-3346a (F)
Tip or Ring Ground Detector
In the ground key or ground start applications a common-mode current detector is used to indicate either a tip- or ring-ground has occurred (ground key) or an offhook has occurred (ground start). The detection threshold is set by connecting a resistor from ICM to VCC. 1000 * VCC/RICM (k) = ITH (mA) where: RICM > 80 k @ VCC = 3.3 V RICM > 150 k @ VCC = 5.0 V Additionally, a filter capacitor across RICM will set the time constant of the detector. No hysteresis is associated with this detector.
Note: Slew rate = 5.65 V/ms; trise = tfall = 23 ms; pwidth = 2 ms; period = 50 ms.
Figure 10. Ringing Waveform Crest Factor = 1.6
80 60 VOLTS (V) 40 20 0 -20 -40 -60 -80 0.00 0.04 0.08 0.12 0.16 0.20 0.02 0.06 0.10 0.14 0.18 TIME (s)
12-3347a (F)
Power Ring
The device offers a ring mode, in which a power ring signal is provided to the tip/ring pair. The standard method of ringing is to perform trapezoidal ringing by Agere Systems Inc.
Note: Slew rate = 10.83 V/ms; trise = tfall = 12 ms; pwidth = 13 ms; period = 50 ms.
Figure 11. Ringing Waveform Crest Factor = 1.2
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L9214A/G Low-Cost Ringing SLIC
Preliminary Data Sheet October 2001
First, calculate the equivalent ringing load resistance at 25 Hz. RLOAD = {(3500 )2 + (2 * * 25 * 16E-6)-2}0.5 RLOAD = 3522 40 Vrms = {(67 - 4)/1.2)} {3522 /(RLOOP + 3522 + 60 )} RLOOP = 1040 Effects such as power supply tolerance and crest factor tolerance can affect this calculation. Crest factor is estimated by the formula: 1 = ------------------------------------------------------------------------------------------------------( 4 x f x CFB x VBAT1 - VOHH ) 1 - ----------------------------------------------------------------------------------------3 x ICS Where: f = ringing frequency; CFB = (CFB1 + CFB2)/2; Ics = 30 A with B3 = 1 and 90 A with B3 = 0; VOHH = 4 V
Supervision (continued)
Power Ring (continued)
The ring signal will appear balanced on tip and ring. That is, the ring signal is applied on both tip and ring, with the signal on tip 180 out of phase from the signal on ring. This operation is shown in Figure 12 below. Ringing loop range is calculated as follows: VRINGLOAD = {(VBATTERY - 4)/Crest Factor} * {RLOAD/(RLOAD + RLOOP + 2 x RPROTECTION)} As a practical example, calculate the maximum dc loop length, assuming the following conditions: Minimum required ring voltage = 40 Vrms VBATTERY = -67 V Trapezoidal ringing, crest factor = 1.2 Protection resistors = 30 each Ring Load = 2 North American REN = 3500 + 16 F Ringing frequency = 25 Hz
L9214
1/2 RLOOP + RPROTECTION GND RING 1V VTIP VRING 3V VBAT 1/2 RLOOP + RPROTECTION PR -1 B1 PT +1 SQUARE WAVE OR PWM SIGNAL
LOAD
12-3532.B (F)
Figure 12. Ring Operation
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Agere Systems Inc.
Preliminary Data Sheet October 2001
L9214A/G Low-Cost Ringing SLIC
Third-Generation Codecs This class of devices includes all ac parameters set digitally under microprocessor control. Depending on the device, it may or may not have data control latches. Additional functionality sometimes offered includes tone plant generation and reception, PPM generation, test algorithms, and echo cancellation. Again, this type of codec may be 3.3 V, 5 V only, or 5 V operation, single-, quad-, or 16-channel, and -law/A-law or 16-bit linear coding selectable. Examples of this type of codec are the Agere T8535/6 (5 V only, quad, standard features), T8537/8 (3.3 V only, quad, standard features), T8533/4 (5 V only, quad with echo cancellation), and the T8531/32 (5 V only, eight- or 16-channel).
Periodic Pulse Metering (PPM)
Periodic pulse metering (PPM), also referred to as teletax (TTX), is applied to the audio input of the L9214. When in the active state, this signal is presented to the tip/ring subscriber loop along with the audio signal. The L9214 assumes that a shaped PPM signal is applied to the audio input.
ac Applications
ac Parameters
There are four key ac design parameters. Termination impedance is the impedance looking into the 2-wire port of the line card. It is set to match the impedance of the telephone loop in order to minimize echo return to the telephone set. Transmit gain is measured from the 2-wire port to the PCM highway, while receive gain is done from the PCM highway to the transmit port. Transmit and receive gains may be specified in terms of an actual gain, or in terms of a transmission level point (TLP), that is the actual ac transmission level in dBm. Finally, the hybrid balance network cancels the unwanted amount of the receive signal that appears at the transmit port.
ac Interface Network
The ac interface network between the L9214 and the codec will vary depending on the codec selected. With a first-generation codec, the interface between the L9214 and codec actually sets the ac parameters. With a third-generation codec, all ac parameters are set digitally, internal to the codec; thus, the interface between the L9214 and this type of codec is designed to avoid overload at the codec input in the transmit direction and to optimize signal to noise ratio (S/N) in the receive direction. Because the design requirements are very different with a first- or third-generation codec, the L9214 is offered with two different receive gains. Each receive gain was chosen to optimize, in terms of external components required, the ac interface between the L9214 and codec. With a first-generation codec, the termination impedance is set by providing gain shaping through a feedback network from the SLIC VITR output to the SLIC RCVN/RCVP inputs. The L9214 provides a transconductance from T/R to VITR in the transmit direction and a single-ended to differential gain from either RCVN or RCVP to T/R in the receive direction. Assuming a short from VITR to RCVN or RCVP, the maximum impedance that is seen looking into the SLIC is the product of the SLIC transconductance times the SLIC receive gain, plus the protection resistors. The various specified termination impedance can range over the voiceband as low as 300 up to over 1000 . Thus, if the SLIC gains are too low, it will be impossible to synthesize the higher termination impedances. Further, the termination that is achieved will be far less than what is calculated by assuming a short for SLIC output to SLIC input.
Codec Types
At this point in the design, the codec needs to be selected. The interface network between the SLIC and codec can then be designed. Below is a brief codec feature summary. First-Generation Codecs These perform the basic filtering, A/D (transmit), D/A (receive), and -law/A-law companding. They all have an op amp in front of the A/D converter for transmit gain setting and hybrid balance (cancellation at the summing node). Depending on the type, some have differential analog input and output stages, +5 V only or 5 V operation, and -law/A-law selectability. These are available in single and quad designs. This type of codec requires continuous time analog filtering via external resistor/capacitor networks to set the ac design parameters. An example of this type of codec is the Agere T7504 quad 5 V only codec. This type of codec tends to be the most economical in terms of piece part price, but tends to require more external components than a third-generation codec. The ac parameters are fixed by the external R/C network so software control of ac parameters is difficult. Agere Systems Inc.
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L9214A/G Low-Cost Ringing SLIC
Preliminary Data Sheet October 2001
Thus, it appears that the solution is to have a SLIC with a low gain, especially in the receive direction. This will allow the codec to operate near its maximum output signal (to optimize S/N), without an external resistor divider (to minimize cost). To meet the unique requirements of both type of codecs, the L9214 offers two receive gain choices. These receive gains are mask programmable at the factory and are offered as two different code variations. For interface with a first-generation codec, the L9214 is offered with a receive gain of 8. For interface with a third-generation codec, the L9214 is offered with a receive gain of 2. In either case, the transconductance in the transmit direction or the transmit gain is 300 , (300 V/A). This selection of receive gain gives the designer the flexibility to maximize performance and minimize external components, regardless of the type of codec chosen.
ac Applications (continued)
ac Interface Network (continued)
In the receive direction, in order to control echo, the gain is typically a loss, which requires a loss network at the SLIC RCVN/RCVP inputs, which will reduce the amount of gain that is available for termination impedance. For this reason, a high-gain SLIC is required with a first-generation codec. With a third-generation codec, the line card designer has different concerns. To design the ac interface, the designer must first decide upon all termination impedance, hybrid balances, and transmission level point (TLP) requirements that the line card must meet. In the transmit direction, the only concern is that the SLIC does not provide a signal that is too hot and overloads the codec input. Thus, for the highest TLP that is being designed to, given the SLIC gain, the designer, as a function of voiceband frequency, must ensure the codec is not overloaded. With a given TLP and a given SLIC gain, if the signal will cause a codec overload, the designer must insert some sort of loss, typically a resistor divider, between the SLIC output and codec input. Note also that some third-generation codecs require the designer to provide an inherent resistive termination via external networks. The codec will then provide gain shaping, as a function of frequency, to meet the return loss requirements. This feedback will increase the signal at the codec input and increase the likelihood that a resistor divider is needed in the transmit direction. Further stability issues may add external components or excessive ground plane requirements to the design. In the receive direction, the issue is to optimize the S/N. Again, the designer must consider all the TLPs. The idea is, for all desired TLPs, to run the codec at or as close as possible to its maximum output signal, to optimize the S/N. Remember noise floor is constant, so the hotter the signal from the codec, the better the S/N. The problem is if the codec is feeding a high-gain SLIC, either an external resistor divider is needed to knock the gain down to meet the TLP requirements, or the codec is not operated near maximum signal levels, thus compromising the S/N.
Design Examples
First-Generation Codec ac Interface Network-- Resistive Termination The following reference circuit shows the complete SLIC schematic for interface to the Agere T7504 firstgeneration codec for a resistive termination impedance. For this example, the ac interface was designed for a 600 resistive termination and hybrid balance with transmit gain and receive gain set to 0 dBm. For illustration purposes, no PPM injection was assumed in this example. This is a lower feature application example and uses single battery operation, fixed overhead, current limit, and loop closure threshold. Resistor RGN is optional. It compensates for any mismatch of input bias voltage at the RCVN/RCVP inputs. If it is not used, there may be a slight offset at tip and ring due to mismatch of input bias voltage at the RCVN/RCVP inputs. It is very common to simply tie RCVN directly to ground in this particular mode of operation. If used, to calculate RGN, the impedance from RCVN to ac ground should equal the impedance from RCVP to ac ground.
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Agere Systems Inc.
Preliminary Data Sheet October 2001
L9214A/G Low-Cost Ringing SLIC
Transmit Gain: gtx = VGSX ---------VT/R
ac Applications (continued)
Design Examples (continued)
Example 1, Real Termination
gtx = The following design equations refer to the circuit in Figure 13. Use these to synthesize real termination impedance. Termination Impedance: VT/R zT = ------------ IT/R zT = 36 Receive Gain: VT/R grcv = ----------VFR grcv = 8 -----------------------------------------------------------------ZT 1 + RRCV + RRCV 1 + -------- - ----------- ----------- RT1 RGP ZT/R 2400 + 2 RP + ---------------------------------RT1 RT1 1 + -------- + ----------RGP RRCV
-RX --------------- x 300 RT2 ZT/R
Hybrid Balance: RXhbal = 20log ----------- - gtx x grcv RHB VGSX hbal = 20log -------------- VFR To optimize the hybrid balance, the sum of the currents at the VFX input of the codec op amp should be set to 0. The expression for ZHB becomes the following: RHB ( k ) = RX -----------------gtx x grcv
RX VGSX
-0.300 V/mA RT2 VITR RCVN RCVP RGP + AV = -1 - L9214 1/4 T7504 CODEC
12-3569 (F)
VFXIN VFXIP
- + +2.4 V
ZT/R
RP TIP
18
- AV = 1 +
- AV = 4 +
RT1 RHB1 RRCV
VS
IT/R + ZT VT/R - RP RING
VFR
CURRENT SENSE
18
Figure 13. ac Equivalent Circuit
Agere Systems Inc.
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L9214A/G Low-Cost Ringing SLIC
Preliminary Data Sheet October 2001
ac Applications (continued)
Design Examples (continued)
Example 1, Real Termination (continued)
VBAT1 RRT1 100 k DBAT1 CRT 1 F RRT2 150 k RIPROG 5.76 k DCOUT CVBAT1 0.1 F
VBAT2 VCC CVBAT2 0.1 F CCC 0.1 F AGND ICM TRGDET ground key not used ITR RGX 4750 VTX CTX 0.1 F TXI RT6 49.9 k VITR L9214A RT3 69.8 k RRCV 60.4 k RGP 26.7 k RCR 5 k CCC1 150 nF RHB1 100 k CC1 0.1 F VFXIN - DX + +2.4 V VFRO DR FSE FSEP MCLK SYNC AND CLOCK PCM HIGHWAY RX
VBAT1 RTFLT
BGND
VBAT2 VCC
100 k
GSX
IPROG (ILOOP = 25 mA) RIREF 28.7 k FUSIBLE RESISTOR OR PTC 30 VBAT1
AGERE L7591
IREF
PR
CC2 0.1 F
RCVP
30 FUSIBLE RESISTOR OR PTC
PT
RCVN
RGN 17.65 k
CF1 CF1 0.22 F CF2 0.1 F CFB1 0.01 F CFB2 0.01 F FROM/TO CONTROL CF2 FB1 FB2 NSTAT B3 B2 B1 B0 ASEL 1/4 T7504 CODEC
CONTROL INPUTS
12-3533.L (F)
Figure 14. Agere T7504 First-Generation Codec; Resistive Termination (5 REN Configuration)
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Agere Systems Inc.
Preliminary Data Sheet October 2001
L9214A/G Low-Cost Ringing SLIC
ac Applications (continued)
Design Examples (continued)
Example 1, Real Termination (continued) Table 20. L9214 Parts List for Agere T7504 First-Generation Codec; Resistive Termination Name Value Tolerance Rating Fault Protection RPT 30 1% Fusible or PTC RPR 30 1% Fusible or PTC Protector Agere -- -- L7591 Power Supply CVBAT1 0.1 F 20% 100 V CVBAT2 0.1 F 20% 50 V DBAT1 1N4004 -- -- CCC 0.1 F 20% 10 V CF1 0.22 F 20% 100 V CF2 0.1 F 20% 100 V dc Profile RIPROG 5.76 k 1% 1/16 W RIREF 28.7 k 1% 1/16 W Ringing/Ring Trip CRT 1.0 F 20% 10 V RRT1 100 k 1% 1/16 W RRT2 150 k 1% 1/16 W CFB1 0.01 F 20% 100 V CFB2 ac Interface RGX RCR CCC1 CTX CC1 CC2 RT3 RT6 RX RHB1 RRCV RGP RGN Optional 0.01 F 20% 100 V Function Protection resistor. Protection resistor. Secondary protection.
VBAT filter capacitor. VBAT filter capacitor. |VBAT2| < |VBAT1|. Reverse current. VCC filter capacitor. Filter capacitor. Filter capacitor. With RIREF, fixes dc current limit. With RIPROG, fixes dc current limit. Ring trip filter capacitor. Ring trip filter resistor. Ring trip filter resistor. With CFB2, slows rate of battery reversal. Sets crest factor of balanced power ring signal. With CFB1, slows rate of battery reversal. Sets crest factor of balanced power ring signal. Sets T/R to VITR transconductance. Compensation resistor. Compensation capacitor. ac/dc separation. dc blocking capacitor. dc blocking capacitor. With RGP and RRCV, sets termination impedance and receive gain. With RX, sets transmit gain. With RT6, sets transmit gain. With RX, sets hybrid balance. With RGP and RT3, sets termination impedance and receive gain. With RRCV and RT3, sets termination impedance and receive gain. Optional. Compensates for input offset at RCVN/RCVP.
4750 5 k 150 pF 0.1 F 0.1 F 0.1 F 69.8 k 49.9 k 100 k 100 k 60.4 k 26.7 k 17.6 k
1% 5% 20% 20% 20% 20% 1% 1% 1% 1% 1% 1% 1%
1/16 W 1/16 W 10 V 10 V 10 V 10 V 1/16 W 1/16 W 1/16 W 1/16 W 1/16 W 1/16 W 1/16 W
Note: TX = 0 dBm, RX = 0 dBm, termination impedance = 600 , hybrid balance = 600 .
Agere Systems Inc.
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L9214A/G Low-Cost Ringing SLIC
Preliminary Data Sheet October 2001
ac Interface Using First-Generation Codec RGX/RTGS/CGS (ZTG): These components give gain shaping to get good gain flatness. These components are a scaled version of the specified complex termination impedance. Note for pure (600 ) resistive terminations, components RTGS and CGS are not used. Resistor RGX is used and is still 4750 . RX/RT6: With other components set, the transmit gain (for complex and resistive terminations) RX and RT6 are varied to give specified transmit gain. RT3/RRCV/RGP: For both complex and resistive terminations, the ratio of these resistors sets the receive gain. For resistive terminations, the ratio of these resistors sets the return loss characteristic. For complex terminations, the ratio of these resistors sets the low-frequency return loss characteristic. CN/RN1/RN2: For complex terminations, these components provide high-frequency compensation to the return loss characteristic. For resistive terminations, these components are not used and RCVN is connected to ground via a resistor.
ac Applications (continued)
Design Examples (continued)
First-Generation Codec ac Interface Network-- Complex Termination The following reference circuit shows the complete SLIC schematic for interface to the Agere T7504 firstgeneration codec for the German complex termination impedance. For this example, the ac interface was designed for a 220 + (820 || 115 nF) complex termination and hybrid balance with transmit gain and receive gain set to 0 dBm. Complex Termination Impedance Design Example The gain shaping necessary for a complex termination impedance may be done by shaping across the Ax amplifier at nodes ITR and VTX. Complex termination is specified in the form:
R2
R1 C
5-6396(F)
RHB: Sets hybrid balance for all terminations. Set ZTG--gain shaping: ZTG = RGX || RTGS + CGS which is a scaled version of ZT/R (the specified termination resistance) in the R1 || R2 + C form. RGX must be 4750 to set SLIC transconductance to 300 V/A.
5-6398(F)
To work with this application, convert termination to the form:
R1
R2
C
RGX = 4750 At dc, CGS and C are open. RGX = M x R1 where M is the scale factor. 4750 M = -------------R1 It can be shown: RTGS = M x R2 and CTGS = C -----M
where: R1 = R1 + R2 R1 R2 = ------- (R1 + R2) R2
2 R2 C = --------------------- C R1 + R2
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Agere Systems Inc.
Preliminary Data Sheet October 2001
L9214A/G Low-Cost Ringing SLIC
ac Applications (continued)
Design Examples (continued)
ac Interface Using First-Generation Codec (continued)
RTGS CGS Rx -IT/R 318.25 RGX = 4750 0.1 F 20 VTX TXI VITR RT6 - + CODEC OP AMP CN RN1 RCVN RCVP RN2 RRCV RGP RT3 RHB
CODEC OUTPUT DRIVE AMP
5-6400.H (F)
Figure 15. Interface Circuit Using First-Generation Codec (Blocking Capacitors Not Shown) Transmit Gain Transmit gain will be specified as a gain from T/R to PCM, TX (dB). Since PCM is referenced to 600 and assumed to be 0 dB, and in the case of T/R being referenced to some complex impedance other than 600 resistive, the effects of the impedance transformation must be taken into account. Again, specified complex termination impedance at T/R is of the form:
R2
Using REQ, calculate the desired transmit gain, taking into account the impedance transformation: 600 TX (dB) = TX (specified[dB]) + 20log ---------REQ TX (specified[dB]) is the specified transmit gain. 600 is the impedance at the PCM, and REQ is the impedance at 600 Tip and ring. 20log ---------- represents the power REQ loss/gain due to the impedance transformation. Note in the case of a 600 pure resistive termination 600 600 at T/R 20log ---------- = 20log --------- = 0. REQ 600
R1 C
5-6396(F)
Thus, there is no power loss/gain due to impedance transformation and TX (dB) = TX (specified[dB]). Finally, convert TX (dB) to a ratio, gtx: TX (dB) = 20log gtx The ratio of RX/RT6 is used to set the transmit gain: RX RT6
---------- = gtx
First, calculate the equivalent resistance of this network at the midband frequency of 1000 Hz. REQ = 2 2 2 2 2 fR2 2 C1 2 - 2 ( 2 f ) C1 R1R2 + R1 + R2 + -------------------------------------------------- ---------------------------------------------------------------------------2 R2 2 C1 2 1 + ( 2 f ) 2 R2 2 C1 2 1 + ( 2 f )
1 ----------------* 318.25 * ---- with a quad Agere codec 20 M
such as T7504: RX < 200 k Agere Systems Inc. 35
L9214A/G Low-Cost Ringing SLIC
Preliminary Data Sheet October 2001
Hybrid Balance Set the hybrid cancellation via RHB. RHB =
-----------------------grcv x gtx
ac Applications (continued)
Design Examples (continued)
ac Interface Using First-Generation Codec (continued) Receive Gain Ratios of RRCV, RT3, RGP will set both the low-frequency termination and receive gain for the complex case. In the complex case, additional high-frequency compensation, via CN, RN1, and RN2, is needed for the return loss characteristic. For resistive termination, CN, RN1, and RN2 are not used and RCVN is tied to ground via a resistor. Determine the receive gain, grcv, taking into account the impedance transformation in a manner similar to transmit gain. REQ RX (dB) = RX (specified[dB]) + 20log ---------600 RX (dB) = 20log grcv Then: 4 grcv = ----------------------------------------------RRCV RRCV 1 + --------------- + --------------RT3 RGP and low-frequency termination 2400 ZTER(low) = -------------------------------------------- + 2RP + 36 RT3- --------------RT3 1 + ----------- + RGP RRCV ZTER(low) is the specified termination impedance assuming low frequency (C or C is open). RP is the series protection resistor. 36 is the typical internal feed resistance. These two equations are best solved using a computer spreadsheet. Next, solve for the high-frequency return loss compensation circuit, CN, RN1, and RN2: 2RP CNRN2 = ------------ CG RTGP 2400 2400 RTGS RN1 = RN2 ------------ ------------- - 1 2RP RTGP There is an input offset voltage associated with nodes RCVN and RCVP. To minimize the effect of mismatch of this voltage at T/R, the equivalent resistance to ac ground at RCVN should be approximately equal to that at RCVP. Refer to Figure 16 (with dc blocking capacitors). To meet this requirement, RN2 = RGP || RT3. 36
RX
If a 5 V only codec such as the Agere T7504 is used, dc blocking capacitors must be added as shown in Figure 16. This is because the codec is referenced to 2.5 V and the SLIC to ground--with the ac coupling, a dc bias at T/R is eliminated and power associated with this bias is not consumed. Typically, values of 0.1 F to 0.47 F capacitors are used for dc blocking. The addition of blocking capacitors will cause a shift in the return loss and hybrid balance frequency response toward higher frequencies, degrading the lower-frequency response. The lower the value of the blocking capacitor, the more pronounced the effect is, but the cost of the capacitor is lower. It may be necessary to scale resistor values higher to compensate for the low-frequency response. This effect is best evaluated via simulation. A PSPICE(R) model for the L9214 is available. Design equation calculations seldom yield standard component values. Conversion from the calculated value to standard value may have an effect on the ac parameters. This effect should be evaluated and optimized via simulation.
Agere Systems Inc.
Preliminary Data Sheet October 2001
L9214A/G Low-Cost Ringing SLIC
ac Applications (continued)
Design Examples (continued)
ac Interface Using First-Generation Codec (continued) Blocking Capacitors
RTGS
CGS Rx
-IT/R 318.25
RGX = 4750 0.1 F 20 VTX TXI VITR RT6 CB1 - + CODEC OP AMP CN RN1 RCVN RCVP RN2 RRCV RGP RT3 RHB
CB2 2.5 V
CODEC OUTPUT DRIVE AMP
5-6401.G (F)
Figure 16. ac Interface Using First-Generation Codec (Including Blocking Capacitors) for Complex Termination Impedance
Agere Systems Inc.
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L9214A/G Low-Cost Ringing SLIC
Preliminary Data Sheet October 2001
ac Applications (continued)
Design Examples (continued)
ac Interface Using First-Generation Codec (continued)
RPWR 2.0 k VBAT1 RRT1 133 k CRT 1 F RRT2 75 k RIPROG 5.76 k DCOUT IPROG (ILOOP = 25 mA) TXI RIREF 28.7 k FUSIBLE RESISTOR OR PTC 30 VBAT1
AGERE L7591
VCC CVBAT1 CVBAT2 0.1 F CCC 0.1 F AGND ICM TRGDET
ground key not used
DBAT1 VBAT1 RTFLT
0.1 F
BGND
VBAT2 VCC
ITR RGX 4750 VTX CTX 0.1 F
RTGS 1.74 k CGS 12 nF RX 115 k GSX
IREF VITR
CC1 RT6 40.6 k 0.1 F L9214A CN 120 pF VFXIN RT3 RHB1 49.9 k 113 k RCVP RN1 127 k RCVN RRCV 59.0 k RGP 54.9 k RN2 47.5 k CC2 0.1 F -
DX + +2.4 V VFRO DR FSE FSEP MCLK SYNC AND CLOCK PCM HIGHWAY
PR
30 FUSIBLE RESISTOR OR PTC
PT
CF1 CF1
CF2
FB1
FB2
NSTAT B3 B2 B1 B0
ASEL 1/4 T7504 CODEC
CONTROL INPUTS
0.22 F
CF2 0.1 F
CFB1 0.01 F
CFB2 0.01 F FROM/TO CONTROL
12-3535.m (F)
Figure 17. Agere T7504 First-Generation Codec; Complex Termination with Power Control Resistor (3 REN Configuration) Table 21. L9214 Parts List for Agere T7504 First-Generation Codec; Complex Termination with Power Control Resistor Name Value Fault Protection RPT 30 RPR Protector 30 Agere L7591 Tolerance 1% 1% -- Rating Fusible or Protection resistor. PTC Fusible or Protection resistor. PTC -- Secondary protection. Function
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Agere Systems Inc.
Preliminary Data Sheet October 2001
L9214A/G Low-Cost Ringing SLIC
Applications (continued)
Design Examples (continued)
ac Interface Using First-Generation Codec (continued) Table 21. L9214 Parts List for Agere T7504 First-Generation Codec; Complex Termination with Power Control Resistor (continued) Name Value Tolerance Power Supply CVBAT1 0.1 F 20% CVBAT2 0.1 F 20% DBAT1 1N4004 -- CCC 0.1 F 20% CF1 0.22 F 20% CF2 0.1 F 20% RPWR 2.0 k 5% dc Profile RIPROG 5.76 k 1% RIREF 28.7 k 1% Ringing/Ring Trip CRING 1.0 F 20% RRT1 133 k 1% RRT2 75 k 1% CFB1 0.01 F 20% CFB2 0.01 F 20% Rating 100 V 50 V -- 10 V 100 V 100 V 2W 1/16 W 1/16 W 10 V 1/16 W 1/16 W 100 V 100 V Function VBAT filter capacitor. VBAT filter capacitor. |VBAT2| < |VBAT1|. Reverse current. VCC filter capacitor. Filter capacitor. Filter capacitor. Power control resistor, provides single battery supply operation. With RIREF, fixes dc current limit. With RIPROG, fixes dc current limit. Ring trip filter capacitor. Ring trip filter resistor. Ring trip filter resistor. With CFB2, slows rate of battery reversal. Sets crest factor of balanced power ring signal. With CFB1, slows rate of battery reversal. Sets crest factor of balanced power ring signal. Sets T/R to VITR transconductance. Gain shaping for complex termination. Gain shaping for complex termination. ac/dc separation. dc blocking capacitor. dc blocking capacitor. With RGP and RRCV, sets termination impedance and receive gain. With RX, sets transmit gain. With RT6, sets transmit gain. With RX, sets hybrid balance. With RGP and RT3, sets termination impedance and receive gain. With RRCV and RT3, sets termination impedance and receive gain. High frequency compensation. High frequency compensation. High frequency compensation, compensate for dc offset at RCVP/RCVN.
ac Interface RGX 4750 RTGS 1.74 k CGS 12 nF CTX 0.1 F CC1 0.1 F CC2 0.1 F RT3 49.9 k RT6 40.2 k RX 115 k RHB1 113 k RRCV 59.0 k RGP 54.9 k CN 120 pF RN1 127 k RN2 47.5 k
1% 1% 5% 20% 20% 20% 1% 1% 1% 1% 1% 1% 20% 1% 1%
1/16 W 1/16 W 10 V 10 V 10 V 10 V 1/16 W 1/16 W 1/16 W 1/16 W 1/16 W 1/16 W 10 V 1/16 W 1/16 W
Note: TX = 0 dBm, RX = 0 dBm, termination impedance = 220 + (820 || 115 nF), hybrid balance = 220 + (820 || 115 nF).
Agere Systems Inc.
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L9214A/G Low-Cost Ringing SLIC
Preliminary Data Sheet October 2001
ac Applications (continued)
Design Examples (continued)
Third-Generation Codec ac Interface Network--Complex Termination The following reference circuit shows the complete SLIC schematic for interface to the Agere T8536 third-generation codec. All ac parameters are programmed by the T8536. Note this codec differentiates itself in that no external components are required in the ac interface to provide a dc termination impedance or for stability. Please see the T8535/6 data sheet for information on coefficient programming.
VBAT1 RRT1 133 k DBAT1 CRT 1 F RRT2 75 k RIPROG 5.76 k DCOUT IPROG (ILOOP = 25 mA) CVBAT1 0.1 F
VBAT2 CVBAT2 0.1 F
VCC CCC 0.1 F AGND ICM TRGDET
ground key not used
VBAT1 RTFLT
BGND
VBAT2 VCC
RCR 2 k ITR RGX 4750 VTX CTX 0.1 F TXI CC1 0.1 F
CCC1 820 pF
RIREF 28.7 k FUSIBLE RESISTOR OR PTC 50 VBAT1 AGERE L7591 50 FUSIBLE RESISTOR OR PTC
IREF VITR L9214G PR RCVP PT RCVN
VFXI
DX0 DR0 DX1 PCM HIGHWAY
VFROP VFRON
DR1
FS CF1 CF1 0.22 F CF2 0.1 F CFB1 0.01 F CFB2 0.01 F FROM/TO CONTROL CF2 FB1 FB2 NSTAT B3 B2 B1 B0 B3 B2 B1 B0 NSTAT SLIC5a SLIC4a SLIC3a SLIC2a SLIC0a DGND VDD BCLK
SYNC AND CLOCK
VDD
1/4 T8536 CODEC
12-3534.Z1 (F)
Figure 18. Third-Generation Codec ac Interface Network; Complex Termination (3 REN Configuration)
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Agere Systems Inc.
Preliminary Data Sheet October 2001
L9214A/G Low-Cost Ringing SLIC
ac Applications (continued)
Design Examples (continued)
Third-Generation Codec ac Interface Network--Complex Termination (continued) Table 22. L9214 Parts List for Agere T8536 Third-Generation Codec Meter Pulse Application ac and dc Parameters; Fully Programmable Name Value Fault Protection RPT 30 RPR 30 Protector Agere L7591 Power Supply CVBAT1 0.1 F CVBAT2 0.1 F DBAT1 1N4004 CCC 0.1 F CF1 0.22 F CF2 0.1 F dc Profile RIPROG 5.76 k RIREF 28.7 k Ringing/Ring Trip CRT 1.0 F RRT1 133 k RRT2 75 k CFB1 0.01 F CFB2 ac Interface RGX RCR CCC1 CTX CC1 0.01 F Tolerance 1% 1% -- 20% 20% -- 20% 20% 20% 1% 1% 20% 1% 1% 20% 20% Rating Fusible or PTC Protection resistor*. Fusible or PTC Protection resistor*. -- Secondary protection. 100 V 50 V -- 10 V 100 V 100 V 1/16 W 1/16 W 10 V 1/16 W 1/16 W 100 V 100 V VBAT filter capacitor. VBAT filter capacitor. |VBAT2| < |VBAT1|. Reverse current. VCC filter capacitor. Filter capacitor. Filter capacitor. With RIREF, fixes dc current limit. With RIPROG, fixes dc current limit. Ring trip filter capacitor. Ring trip filter resistor. Ring trip filter resistor. With CFB2, slows rate of battery reversal. Sets crest factor of balanced power ring signal. With CFB1, slows rate of battery reversal. Sets crest factor of balanced power ring signal. Sets T/R to VITR transconductance. Compensation resistor. Compensation capacitor. ac/dc separation. dc blocking capacitor. Function
4750 10 k 270 pF 0.1 F 0.1 F
1% 5% 20% 20% 20%
1/16 W 1/16 W 10 V 10 V 10 V
* For loop stability, increase to 50 minimum if synthesizing 900 or 900 + 2.16 F termination impedance.
Agere Systems Inc.
41
L9214A/G Low-Cost Ringing SLIC
Preliminary Data Sheet October 2001
Outline Diagrams
28-Pin SOG
Note: The dimensions in these outline diagrams are intended for informational purposes only. For detailed drawings to assist your design efforts, please contact your Agere Sales Representative.
L N
B
1 PIN #1 IDENTIFIER ZONE W
H SEATING PLANE 0.10 1.27 TYP 0.51 MAX 0.28 MAX 0.61
Package Description SOG (small outline gull-wing)
Number of Pins N 28
Maximum Length L 18.11
Package Dimensions Maximum Width Maximum Width Maximum Height Without Leads Including Leads Above Board B W H 7.62 10.64 2.67
5-4414
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Agere Systems Inc.
Preliminary Data Sheet October 2001
L9214A/G Low-Cost Ringing SLIC
Outline Diagrams (continued)
32-Pin PLCC
Note: The dimensions in this outline diagram are intended for informational purposes only. For detailed schematics to assist your design efforts, please contact your Agere Sales Representative.
12.446 0.127 11.430 0.076 PIN #1 IDENTIFIER ZONE 1 30
4
5
29
13.970 0.076 14.986 0.127
13
21
14
20
3.175/3.556 SEATING PLANE 0.10
1.27 TYP
0.38 MIN TYP 0.330/0.533
5-3813r2 (F)
Agere Systems Inc.
43
L9214A/G Low-Cost Ringing SLIC
Preliminary Data Sheet October 2001
Outline Diagrams (continued)
48-Pin MLCC
Dimensions are in millimeters. Notes: The dimensions in this outline diagram are intended for informational purposes only. For detailed schematics to assist your design efforts, please contact your Agere Sales Representative. The exposed pad on the bottom of the package will be at VBAT1 potential.
7.00 3.50 6.75 3.375 0.50 BSC
1 2 3
C
C CL
PIN #1 IDENTIFIER ZONE
6.75 7.00
DETAIL A VIEW FOR EVEN TERMINAL/SIDE
0.18/0.30
0.00/0.05 SECTION C-C DETAIL A 12 SEATING PLANE 0.20 REF 11 SPACES @ 0.50 = 5.50 0.24/0.60 0.18/0.30 0.13/0.23 0.08 0.01/0.05 0.65/0.80 1.00 MAX
0.24/0.60
0.20/0.45
5.10 0.15
3 2 1
0.30/0.45
EXPOSED PAD
0.50 BSC
0195
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Agere Systems Inc.
Preliminary Data Sheet October 2001
L9214A/G Low-Cost Ringing SLIC
Outline Diagrams (continued)
48-Pin MLCC, JEDEC MO-220 VKKD-2
Dimensions are in millimeters. Notes: The dimensions in this outline diagram are intended for informational purposes only. For detailed schematics to assist your design efforts, please contact your Agere Sales Representative. The exposed pad on the bottom of the package will be at VBAT1 potential.
7.00 3.50 PIN #1 IDENTIFIER ZONE
CL
0.50 BSC 3.50 INDEX AREA (7.00/2 x 7.00/2) 7.00 DETAIL A VIEW FOR EVEN TERMINAL/SIDE
0.18
0.23
TOP VIEW
1.00 MAX SEATING PLANE 0.20 REF 0.08 0.02/0.05 DETAIL B 0.23
0.18
SIDE VIEW
11 SPACES @ 0.50 = 5.50 DETAIL A 0.18/0.30
0.30/0.50
2.50/2.625 5.00/5.25
3 2 1
EXPOSED PAD 0.50 BSC DETAIL B
BOTTOM VIEW
0195
Agere Systems Inc.
45
L9214A/G Low-Cost Ringing SLIC
Preliminary Data Sheet October 2001
Ordering Information
Device Part No. LUCL9214AAJ-D LUCL9214AAJ-DT LUCL9214AAU-D LUCL9214AAU-DT LUCL9214ARG-D LUCL9214ARG-DT LUCL9214GAJ-D LUCL9214GAJ-DT LUCL9214GAU-D LUCL9214GAU-DT LUCL9214GRG-D LUCL9214GRG-DT Description SLIC Gain = 8 SLIC Gain = 8 SLIC Gain = 8 SLIC Gain = 8 SLIC Gain = 8 SLIC Gain = 8 SLIC Gain = 2 SLIC Gain = 2 SLIC Gain = 2 SLIC Gain = 2 SLIC Gain = 2 SLIC Gain = 2 Package 28-Pin SOG*, Dry-bagged 28-Pin SOG*, Dry-bagged, Tape and Reel 32-Pin PLCC, Dry-bagged 32-Pin PLCC, Dry-bagged, Tape and Reel 48-Pin MLCC, Dry-bagged 48-Pin MLCC, Dry-bagged, Tape and Reel 28-Pin SOG*, Dry-bagged 28-Pin SOG*, Dry-bagged, Tape and Reel 32-Pin PLCC, Dry-bagged 32-Pin PLCC, Dry-bagged, Tape and Reel 48-Pin MLCC, Dry-bagged 48-Pin MLCC, Dry-bagged, Tape and Reel Comcode 108553892 108553900 108697905 108697913 109058636 109058644 108560723 108560731 108698309 108698317 109058651 109058669
* Please contact your Agere Sales Representative for availability.
UL is a trademark of Underwriters Laboratories, Inc. IEC is a registered trademark of the International Electrotechnical Commission. IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc. PSPICE is a registered trademark of MicroSim Corporation. Telcordia Technologies is a trademark of Bell Communications Research, Inc.
For additional information, contact your Agere Systems Account Manager or the following: INTERNET: http://www.agere.com E-MAIL: docmaster@agere.com N. AMERICA: Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA: Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Harbour City, Kowloon Tel. (852) 3129-2000, FAX (852) 3129-2020 CHINA: (86) 21-5047-1212 (Shanghai), (86) 10-6522-5566 (Beijing), (86) 755-695-7224 (Shenzhen) JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 778-8833, TAIWAN: (886) 2-2725-5858 (Taipei) EUROPE: Tel. (44) 7000 624624, FAX (44) 1344 488 045
Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application.
Copyright (c) 2001 Agere Systems Inc. All Rights Reserved
October 2001 DS01-144ALC (Replaces DS00-342ALC)

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